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摘要：本課題利用Verilog硬件描述語言在由Altera公司開發(fā)的QUARTUS II平臺上，設(shè)計(jì)并實(shí)現(xiàn)一個(gè)基于FPGA的單周期CPU。該CPU能夠?qū)崿F(xiàn)MIPS指令系統(tǒng)中的11條代表性指令，這11條MIPS指令集選取了R型，I型，J型三種類型指令，既有算術(shù)/邏輯運(yùn)算指令，又有取數(shù)/存數(shù)指令；既有條件轉(zhuǎn)移指令，又有無條件轉(zhuǎn)移指令；既有需要考慮溢出判斷的指令，又有無需考慮溢出的指令；既有對帶符號數(shù)判斷大小的指令，又有對無符號數(shù)判斷大小的指令，基本涵蓋了所有指令的基本實(shí)現(xiàn)技術(shù)，因此非常具有代表性。 在設(shè)計(jì)過程中，本課題采用了自上而下的模塊化設(shè)計(jì)思路，根據(jù)cpu指令執(zhí)行過程中相關(guān)部件的邏輯算術(shù)功能進(jìn)行了數(shù)據(jù)通路和控制部件的設(shè)計(jì)。并就各部件的功能編寫了相關(guān)代碼使得指令在運(yùn)行過程中，各部件能各司其職，正確執(zhí)行。 最后，本課題還選用powerbuilder制作了該單周期CPU設(shè)計(jì)過程的展示軟件。 關(guān)鍵詞：單周期CPU、 verilog HDL語言、 MIPS指令集、 Powerbuilder
Abstract：On the basis of QUARTUS II which is developed by Altera, this subject is the design and implementation of a FPGA-based single-cycle CPU, using Verilog hardware description language. This CPU can achieve 11 representative instructions of the MIPS instruction set. The 11 MIPS instruction set selected three types of instruction—R-type, I-type and J-type. It contained the arithmetic / logic operation instruction as well as the load/poke instruction; the conditional transfer instruction as well as the unconditional transfer instruction; the overflow considered instruction as well as the overflow unconsidered instruction; and the instruction to judge signed numbers as well as the instruction to judge unsigned numbers. It is representative for it covering all the basic implementation technology instructions. In the design process, the subject adopts a top-down design idea in modules and designs the data path and control unit according to the logical arithmetic function of related components during the CPU command execution. Relevant codes have been written based on the function of each part to make sure the components can perform their duties correctly in the operation process. Finally, the project selected powerbuilder to design the software to display the design procedure of the single-cycle CPU. Key words: single-cycle CPU 、verilog HDL language、MIPS instruction set、Powerbuilder
本課題是在QUARTUS II的平臺上運(yùn)用verilog語言，以實(shí)現(xiàn)MIPS指令系統(tǒng)中具有代表性的11條MIPS指令為目的，設(shè)計(jì)并實(shí)現(xiàn)的單周期cpu。 在完成這份課題的時(shí)間里。在指導(dǎo)老師的悉心指導(dǎo)和同小組成員的幫助之下，我通過認(rèn)真學(xué)習(xí)材料，積極動手實(shí)踐，最終成功的完成了任務(wù)。 在這一段簡單而又充實(shí)的時(shí)間里，我受益良多，起初對于cpu的知識知之甚少，對于QUARTUSII更是一無所知，從開始就產(chǎn)生了很大的畏難情緒。但是通過指導(dǎo)老師的悉心講解與指導(dǎo)，我漸漸對MIPS常用的指令系統(tǒng)，單周期CPU的工作原理與邏輯功能實(shí)現(xiàn)有了較深的認(rèn)識。并完成了任務(wù)。
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