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| 折扣與優(yōu)惠：團購最低可5折優(yōu)惠 - 了解詳情 | 論文格式：Word格式(*.doc) |  |
摘要 在近代，濾波器逐漸成為電信設(shè)備和各類控制系統(tǒng)中，一個不可缺少的組成部分，應用已經(jīng)極為廣泛，適用于通信處理、語音處理、圖像處理、自動控制，在軍事、醫(yī)療設(shè)備和家用電器上等各方各面。早期的濾波器只能滿足設(shè)計簡單、結(jié)構(gòu)簡便的要求，通過不斷地研究，衍生出一個新的分支，就是數(shù)字濾波器。 自從FPGA在約二十世紀出現(xiàn)以來，為數(shù)字濾波器的設(shè)計和實現(xiàn)創(chuàng)造出一條嶄新的道路。不過，單獨設(shè)計一個滿足技術(shù)指標的數(shù)字濾波器是一件有挑戰(zhàn)性的設(shè)計任務，需要一些軟件的輔助，例如，MATLAB、QUARTUSII等軟件。 在論文中，設(shè)計是基于FPGA的FIR數(shù)字濾波器，設(shè)計過程中實現(xiàn)低通濾波，采樣頻率為45kHz，截止頻率為10.5kHz，通帶截止頻率處的幅值衰減小于6db，輸入輸出為8位二進制數(shù)。 論文首先介紹了本文的研究背景，然后介紹現(xiàn)場可編程門陣列（FPGA）和硬件描述語言（VHDL），之后介紹了數(shù)字濾波器的設(shè)計原理，并提出本文采用的設(shè)計方法，最后對設(shè)計進行仿真。仿真結(jié)果表明：本17階FIR數(shù)字濾波器設(shè)計能夠?qū)崿F(xiàn)截止頻率為10.5kHZ的低通濾波。 關(guān)鍵詞：數(shù)字信號處理；數(shù)字濾波器；現(xiàn)場可編程門陣列；硬件描述語言
Abstract Nowadays, the filter is the indispensable part of the tele-communication equipment and types of control system and it has been widely used. It adapts to use in the communication processing, voice processing, image processing, auto-control. In early period, the filter’s circuit was simple, so it just could design something easily. Though the designers research again and again on the filters’ design, a new branch is created which is the digital filter. Since the FPGA appeared nearly in the twentieth century, it has created a new way for the design and implementation of the digital filter. However, designing a digital filter to meet the technical indicators is a challenging task by myself. I need some software to assist me, for example, MATLAB, QUARTUS II and others. In the papers, the design is the FIR digital filter based on FPGA to implement the low-pass filter which sampling frequency is 45kHz, cut-off frequency is 10.5kHz, pass-band amplitude attenuation at the cut-off frequency is less than 6db, input and output is 8 bit in two-tier system. Paper first introduces the research background, then it describes field programmable gate array (FPGA) and hardware description language (VHDL). Next comes the principle and design of digital filter and it proposes the design method, finally the design can be simulated. The result of the design’s simulation shows that, the 17-order FIR digital filter can implement the low-pass filter which cut-off frequency is 10.5kHz. Keyword: Digital signal processing; Digital filter; FPGA; Hardware description language.
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